Low-Voltage, Inductorless Folded Down-Conversion Mixer in 65nm CMOS for UWB Applications

Sven Karsten Hampel, Oliver Schmitz, Marc Tiebout, Ilona Rolfes

Radio Frequency Integrated Circuits Symposium (RFIC 2009)in conjunction with the International Microwave Symposium, pp. 119-122, Boston, Massachusetts, June 7-9, 2009


This paper presents the design and implementation of a low-voltage down-conversion mixer in 65 nm CMOS technology for UWB applications. The folded circuit topology with AC-coupled inverter based RF transconductance stage operates under low voltage conditions of 1.2 V with a peak gain of 14.5 dB and a 3-dB-bandwidth from 1 GHz to 10.5 GHz with 1 dBm LO power. The input referred compression point is better than -16.5 dBm with an oIP3 of 7 dBm at 2 GHz. The minimum DSB noise figure is 6.5 dB with a flicker-noise corner frequency of 2 MHz. The mixer draws 12 mA from a power supply of 1.2 V leading to a power dissipation of only 14.4 mW.

[IEEE Library]

Tags: CMOS, mixer