course: Introduction to Hardware Reverse Engineering
- teaching methods:
- lecture with integrated tutorials
- Moodle, computer based presentation, black board and chalk
- responsible person:
- Prof. Dr.-Ing. Christof Paar
- Prof. Dr.-Ing. Christof Paar (ETIT), M. Sc. Nils Albartus (ETIT), M. Sc. Steffen Becker (ETIT)
- offered in:
- winter term
dates in winter term
- lecture with integrated tutorials Thursdays: from 10:15 to 11.45 o'clock in ID 04/471
- lecture with integrated tutorials Fridays: from 12:15 to 13.45 o'clock in ID 04/445
The students are familiar with the fundamental aspects of complex logic circuit layout. This involves the comprehension of ASIC and FPGA architectures and their corresponding workflows, as well as the application of the associated tools and utilization of Hardware Description Languages (HDLs). Furthermore, the students have a profound theoretical understanding of the several steps required for the hardware reverse engineering process and know their implications. Last not least, students gather first practical experiences in gate-level netlist reverse engineering.
The so-called reverse engineering of devices plays an important role for legitimate users and hackers. On the one hand, reverse engineering can support companies and governments to discover IP (intellectual property) fraud or targeted manipulations. On the other hand, hackers utilize reverse engineering to steal and copy others' IP, or to implement backdoors into software or hardware circuits.
To get started with hardware reverse engineering successfully, it is important to understand the basic concepts of (forward) engineering integrated circuits. Therefore, the content of this lecture is structured into two parts:
Part I: Basic Principles of VLSI Design (VLSI stands for Very-large scale integration)
- Introduction to ASIC and FPGA architectures
- Introduction to combinatorial circuits
- Sequential circuits
- Hardware Description Languages (HDLs)
- ASIC and FPGA workflows
Part II: Hardware Reverse Engineering
- PCB analysis, delayering, imaging, and post-processing
- FPGA bitstreasm reverse engineering
- Gate-level netlist reverse engineering
Contents of the lecture "Informatik 3 - Digitaltechnik und Rechnerarchitektur"
The examination of this class is spilt into a written Exam (60%) and projects (40%). 15% bonus points can be reached in addition.
In parallel to the lecture we will conduct a research project. The participation is voluntary and will be rewarded with 50€.